[Targeting] 5G Design: From Waveform Generation to Hardware Implementation and Verification
Real-time processing of 5G New Radio (NR) waveforms is a complex undertaking. It requires the processing power of an FPGA, and the flexibility of a processor. Learn how to get started using MATLAB and Simulink to refine a 5G NR receiver algorithm so it can be deployed across the FPGA fabric and the ARM processor on a Xilinx Zynq SoC.
Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.
- Generating 5G waveforms
- Developing a 5G signal detection algorithm
- Hardware-software co-design
- FPGA reference receiver from A/D to resource grid
- MATLAB algorithm to embedded C code
- Real-time debugging
- Example Projects
About the Presenters
As a senior applications engineer, Jeff Miller focuses on supporting customers for adopting HDL code generation and 5G/LTE technology. Customer projects have included HDL designs for high-performance FFT, FIR, Matrix Mathematics, Encryption, Custom Floating Point, and LTE receivers. Prior to joining MathWorks, Jeff worked at Applied Signal Technology doing Signal Intelligence, and at Morphics Technology doing commercial wireless communications. Jeff has a Master’s of Electrical Engineering from Georgia Tech and a Master’s of Education from the University of Arizona.
Tom Mealey is a Senior Application Engineer at MathWorks. He supports customers in adopting Model-Based Design to accelerate the design and deployment of complex control and algorithmic applications including communications, radar, computer vision, audio, and deep learning. He is an expert on the design and implementation of applications targeting the Xilinx Zynq platform and other SoC devices. Prior to working at MathWorks, Tom worked at the Air Force Research Laboratory’s Sensors Directorate, where he was involved in projects implementing digital signal processing on FPGAs and SoCs. Tom earned his B.S. in Computer Engineering from the University of Notre Dame and his M.S. in Electrical Engineering from the University of Dayton.
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